The present invention is a clock generator circuit using semiconductor integrated circuits.
A clock generator circuit is a circuit which stably generates a clock signal having a frequency higher than an input clock signal.
In recent years, a clock having an extremely high frequency has been required as data processing speed has dramatically increased. Thus, a method is conceived in which a circuit for generating a clock signal having a high frequency is directly mounted on a board. However, since waveform distortions inevitably occur in this method, there is a limit to the frequency, and the upper limit is about 50 MHZ. Further, in personal computers, the types of clocks usable on the board are limited, and the use of clocks other than those requires additional crystal oscillators, but this is a problem in the point of cost. Accordingly, it is needed to previously mount an external clock signal generator circuit of a relatively low frequency on the board, and form a clock generator circuit for performing a conversion to increase the frequency on a chip.
Conventionally, the clock generator circuit consists of a PLL (Phase Lock Loop) which is an analog circuit. The clock generator by the analog PLL has good stability in operation, and has a high precision as a whole in the point that it is finely adjustable, and thus it is widely used. The advantage of the analog clock generator is that it has a high precision as described above. High precision is a large advantage of the clock generator, a circuit which generates a clock signal with a precision of one several tens of thousandth second. However, the analog clock generator has the following disadvantages.
First, it takes much time for the frequency to converge on a stable state. This is because one reason for the high precision of the analog clock generator is based on the fact that it can be finely adjusted. However, the amount of one adjustment needs to be made small to exhibit such merit, and as a result, the convergence time becomes long.
Second, there is also a problem with the design and implementation. That is, a power supply for analog equipment and a GND pin need to be prepared for using the analog clock generator, and registers and capacitors need to be prepared in addition to chips. Moreover, the whole design must be renewed if the technology being used changes, and thus it is not suitable for the process in which products are made by trial and error.
The merit obtainable by the construction of the clock generator using a digital circuit resides in that the above disadvantages of the clock generator by an analog circuit can be eliminated. That is, since digital is essentially binary, attention need not be paid to detail differently from analog. By this, the merit of an analog circuit that fine adjustment can be made may be lost to some extent in the clock generator by a digital circuit, but the merit in the aspect of design and implementation is unmeasurable.
In the conventional digital circuit, however, a signal having a frequency larger than the input clock cannot be generated without using a delay element. Further, the extent of the delay by the delay element varies depending on the conditions such as temperature and voltage. Accordingly, to form a stable clock generator by a digital circuit, a function is required for self-compensating the variation due to such factors.
Hereinafter in the specification of this application, the single circuit for generating a clock signal is referred to as a clock generator, and a circuit system for generating a stable clock signal by combining clock generators is referred to as a clock generator circuit.